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SDR - Software Defined Radio Technology

Introduction

Modern, but conventional radio communication systems typically target one specific region of the available radio spectrum for transmitting wanted signal information (Tx data or voice) or receiving this information (Rx data or voice). Although these radio communications may span a wide range of frequencies, they typically only process one radio channel at a time. The "Software Defined Radio" or SDR concept seeks to avoid this limitation by digitally processing wide allocations of spectral bandwidth containing multiple signals of interest. Further, conventional radio communication systems are usually inflexible in the modulation formats and associated signal bandwidths that can be accommodated. For example, a communications receiver may allow reception of SSB, DSB or AM but be incapable of processing digital modulation formats such as DQPSK, PSK, QAM, OFDM or CDMA. This restriction is usually based on cost constraints and the requirements envisioned for the final end user. Also, component technology and signal processing technology is still emerging for SDR applications.

The Ultimate Software Defined Radio technology should offer (a minimum of) the following key features,

bulletSimultaneous Processing Of Multiple Radio Signals at different radio frequencies.
bulletProcessing such Signals Across Multiple Non Contiguous Radio Spectrum e.g. Medium Wave, Short-wave HF, VHF, UHF and Microwave.
bulletArbitrary Modulation Format Capability - All necessary modulation and demodulation software is contained in one system.
bulletSimultaneous Signal Bandwidth Processing Options - capability to process signals with unrelated modulation bandwidth and data rates in parallel.
bulletArbitrary Signal Bandwidth Capability - defined by software in the digital domain.
bulletSimultaneous Signal Bandwidth Processing Options - capability to process signals with unrelated modulation bandwidth and data rates in parallel.  
bulletSoftware Upgrade Potential - Ability to enhance performance or functionality (in real time without Loss Of Service i.e. no LoS) with software upgrades (preferably over the air upgrade potential).  

Although conventional radio communication systems can accomplish "one modulation type" at a time based on a smorgasbord of possible options, the ability to simultaneously cover all possible formats, bandwidths and data rates is still elusive. A full SDR system would automatically incorporate all possible combinations simultaneously and based on digital processing technologies.

Surprisingly, the RF hardware necessary to make a usable SDR is already available. The high speed mixed signal technology (Analog to Digital "ADC" and Digital to Analog" DAC converters is continually advancing. Notable in this technology race is Maxim-ic with their MAX109 8 Bit, 2.2 GHz sampling ADC  

http://datasheets.maxim-ic.com/en/ds/MAX109.pdf

and an impressive MAX5881 16 Bit, 4.3 GHz sampling DAC

http://www.maxim-ic.com/quick_view2.cfm/qv_pk/5607

 

These "state of the art" devices will be used as example components in feasibility studies under the following last two headings,

The Multiple User Software Configurable Arbitrary Format (MUSCAF) represents an old presentation I made for RAWCON 98 in Colorado, 1998. This showed the feasibility of using conventional components at the time to make a PMR compatible receiver with 12 channel processing capability within a 200 kHz "roofing" bandwidth. 

The article "Direct RF Signal Acquisition" i.e. DRFSA (coming soon) will examine to feasibility of directly capturing a complete RF input spectrum from DC to 1 GHz or higher and present some predictions on overall receiver performance in relation to today's Type Approval standards.

A companion article "Direct RF Signal Synthesis i.e. DRFSS (coming soon) will examine to feasibility of directly generating a complete RF output spectrum from DC to 1 GHz or higher and present some predictions on overall transmitter performance in relation to today's Type Approval standards.

It should be noted that current Type Approval standards may not set a barrier to some potential application. For example, in accident and emergency situations, such as caused by adverse weather, earthquakes, comet collision or human aggression, the ambition for secure communication may well outweigh current spectral mask limitations imposed from a "good neighbor" strategy in congested spectral areas. Under adverse emergency situations, most radio infrastructure systems may be rendered inoperable. In this case, any usable "ad hoc radio deployment" will be welcome.

I illustrate this in another related web article that can be found here, UHF Optic Transfer

Interestingly, ADC and DAC technology may not represent the limiting factor in SDR technology. Bit resolution and sample rate limits are continually improving. Two relatively serious technology areas still need to be addressed,

bulletADC and DAC Clock jitter or "phase noise" - limits ultimate SNR in a time sampled system to 20 Log10{ 2 pi FRF  dtRMS } where FRF = RF input frequency in Hz and dTRMS = RMS Clock Jitter in seconds. A "good" low jitter source can be expected to have a clock jitter performance of dTRMS < 0.2 Pico-seconds,
bulletArbitrary (Non Integer Related!) Data and Clock Interpolation - Typical design approaches "lock" the various internal clock frequencies to an integer M/N relationship with actual data and clock rates. This represents a serious limitation in any SDR architecture as many data and clock rates may need to be processed simultaneously without being constrained to any overall integer frequency relationship. 

The effect of clock jitter can be illustrated by example. Consider a 14 Bit ADC with a clock sample rate of Fs = 200 MHz and associated clock jitter of dTRMS = 0.2 ps . Let us assume it is now used to sub-sample an input signal on its second upper alias zone of 450 MHz. The ultimate SNR from a 14 Bit ADC would be predicted from SNRdB = 6.02 N + 1.76 = 86.0 dB, measured in a total bandwidth of Fs/2 = 100 MHz. In comparison, the ultimate SNR predicted from 0.2 ps clock jitter would only be 65 dB. This SNR limit is comparable to the SNR expected from an 11 Bit device. This renders the "left over" 3 Bits available in the 14 Bit ADC example to be relatively useless. Ultra low jitter clock oscillator design is therefore essential for high speed, high resolution mixed signal devices used for direct RF digitization. (Note: Clock jitter is related to oscillator phase noise, but not directly. For example, jitter can be improved by adding a band pass filter between the oscillator signal output and its conversion to a digital clock output (i.e. restrict total noise energy before digitizing to 0,1) without affecting standard phase noise measurement metrics).

Note: The internally generated clock jitter for the MAX108 8 Bit 1.5 GHz ADC, mentioned previously, is specified as having 0.5 ps RMS clock jitter. Its recent 8 Bit 2.2 GHz ADC cousin - the MAX109 is specified as having 0.2 ps RMS internally generated clock jitter.

The second concern is really just one of conventional "standard practice" in the approach to digital modulation. For example, a given digital constellation (BPSK, QPSK, DQPSK, FSK, QAM, etc) may be constructed based on "M Samples Per Symbol". If the Symbol rate is 1 M Symbol / second then the sample rate has to be 4 M Samples / second. How could such a system simultaneously accommodate additional unrelated data rates at say 27.9723491 k Symbols / second? Clearly this approach must either be abandoned, or an efficient "interpolation" processing block is introduced for "clock and data rate interfacing".

Although certainly not recommended, a hardware intensive approach could be used. For example a DAC could generate an output at one data rate, be followed by a hardware interpolating filter and then be digitized by an ADC at another data rate. The issue of different clock frequencies would still need to be addressed and the cost and complexity overhead with, say, a 10,000 channel system would be prohibitive!

Clearly this interpolation must be accomplished by digital software techniques. A SDR system cannot expect all signals needing to be processed to have simple integer frequency relationships. Simply re-sampling digital values results in a serious SNR degradation - effectively a jitter noise mechanism. The incoming digital signal could be interpolated to a higher sample rate by an integer M and then decimated to a lower sample rate by an integer N (overall interpolation ratio = M/N) but this is computationally expensive and the exact integer values for M and N may not be readily available. 

The conclusion is obvious - a SDR approach must simply "bite the bullet" and assume aperiodic signals as standard, or incorporate flexible data rate conversion algorithms with low computational overhead and high SNR performance.

Note: Very few applications actually require full SDR functionality and performance. It is always important to match technology to the required end user application. Many radio systems, for example may benefit from having some modulation format and bandwidth flexibility but have little if any need for simultaneous arbitrary modulation format capability. Alternatively, multiple channel operation may be required but within a smaller defined region. Even then, a common modulation format and data rate may expected within these multiple channel groups.

Software Defined Radio - Direct RF Signal Synthesis (DRFSS) Transmitter Architectures

A DRFSS Transmitter transmitter represents the "ultimate" SDR concept aimed at maximum programmable flexibility. A transmit superhet based architecture can be considered as a "sub set" of the DRFSS approach whereby the RF signal is synthesized at an IF frequency and then frequency converted to the final RF output frequency in one or more stages. The superhet approach can also, in principle, be substituted with an Analog IQ to RF architecture and have similar overall functionality and performance. These other approaches still require technical resolution of issues relating to efficient linear wide band RF power amplification and specific digital implementation strategies, but performance demands on the mixed signal analog to digital interface are relaxed in exchange for reduced spectral bandwidth processing capability.

More information on SDR DRFSS Transmitters is here: SDR DRFSS Tx

 

Software Defined Radio - Direct RF Signal Acquisition (DRFSA) Receiver Architectures

A DRFSA Receiver represents the "ultimate" SDR concept aimed at maximum programmable flexibility. A transmit superhet based architecture can be considered as a "sub set" of the DRFSA approach whereby the RF signal is frequency down converted to a lower IF frequency and then digitized. A Direct Conversion RF to IQ architecture is equally feasible - both of these approaches relax the demands placed on the mixed signal analog to digital interface in exchange for reduced spectral bandwidth processing capability.

In all cases this "wide instantaneous bandwidth" approach requires multiple channel processing in the digital domain. Consequently, a potentially high signal peak to average power ration must be expected (similar requirement to a DRFSS Transmitter). ADC devices tend to have relatively harsh performance degradation with even minor amounts of input overdrive so the relative incidence of this needs to be managed. Some form of fast acting AGC (fast attack, slow decay) system may be advantageous to result in a more graceful and gradual degradation with high peak to average input spectra.

More information on SDR DRFSA Receivers is here: SDR DRFSA Rx  

 

Summary

 

 

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Ian R Scott 2007 - 2008